Required arrival is 1.20 ns and actual is 1.05 ns. Setup slack?
A Minus 0.15 ns
B Plus 0.15 ns
C Plus 2.25 ns
D Zero ns
Answer: B. Plus 0.15 ns. Setup slack is required time minus arrival time: 1.20−1.05=0.15 ns.
What does −0.08 ns setup slack indicate?
A Timing margin
B Hold pass
C Clock gating
D Setup violation
Answer: D. Setup violation. Negative setup slack means the path misses its required arrival time by 0.08 ns.
With zero skew and uncertainty, a register path’s minimum period covers which sum?
A Only wire capacitance
B Only hold time
C Clock-to-Q, logic, setup
D Only clock skew
Answer: C. Clock-to-Q, logic, setup. With zero skew and uncertainty, the nominal minimum period covers launch clock-to-Q delay, maximum combinational delay, and capture setup time.
Hold timing is violated when data reaches the capture pin how?
A Too soon after edge
B Too late for setup
C Exactly one cycle later
D After fabrication
Answer: A. Too soon after edge. Hold violations occur when the minimum data path is too short relative to the clock relationship.
When the capture clock arrives later, which checks improve and worsen?
A Hurts setup, helps hold
B Helps both checks
C Helps setup, hurts hold
D Hurts both checks
Answer: C. Helps setup, hurts hold. Positive capture skew gives more setup time but tightens the hold requirement.
Why are two flip-flops used in a basic single-bit synchronizer?
A Increase bus width
B Allow metastability to resolve
C Reduce logic depth
D Change signal polarity
Answer: B. Allow metastability to resolve. The first stage may become metastable; the second gives it extra time to resolve before use.
Does a synchronizer make metastability impossible?
A Yes, always
B Only at low frequency
C Only for reset
D No, it lowers risk
Answer: D. No, it lowers risk. Synchronizers reduce the probability that metastability propagates; they cannot guarantee it never occurs.
Gray-coded counters change how many bits between adjacent values?
A One bit
B Two bits
C All bits
D No bits
Answer: A. One bit. Gray coding changes one bit between successive count values, reducing ambiguity during asynchronous sampling.
For a positive-edge clock, an integrated clock-gating latch is transparent when?
A Clock is high
B Clock is low
C Reset is high
D Data is changing
Answer: B. Clock is low. The latch captures the enable while the clock is low and holds it during the active high phase to avoid glitches.
Power-gated outputs use isolation cells to prevent what?
A Clock skew increasing
B DRC rules changing
C Unknown values propagating
D Metal resistance vanishing
Answer: C. Unknown values propagating. Isolation clamps signals from a shut-down block so unknown or floating values do not corrupt active logic.
Retention cells preserve what during a power-gated state?
A Selected state bits
B All clock edges
C Routing geometry
D Photoresist patterns
Answer: A. Selected state bits. Retention cells keep selected state while the main logic supply is off.
How are scan flip-flops connected during scan operation?
A Parallel capacitor bank
B Clock tree
C Power grid
D Serial shift register
Answer: D. Serial shift register. Scan mode links scan-capable flip-flops into a shift path for test access.
The stuck-at fault model assumes a node is fixed at what?
A Unknown voltage only
B Half supply always
C Logic zero or one
D Clock edge
Answer: C. Logic zero or one. A stuck-at fault models a signal line permanently fixed at logic 0 or logic 1.
ATPG generates what to detect modeled circuit faults?
A Mask layers
B Test patterns
C Clock trees
D PDK models
Answer: B. Test patterns. Automatic test-pattern generation finds input patterns that expose modeled faults.
Post-route parasitic extraction feeds which analyses?
A Timing and power
B Only RTL parsing
C Only lithography
D Only logic equations
Answer: A. Timing and power. Extracted wire parasitics improve post-layout timing and power estimates.
Metal fill is added mainly to satisfy which requirement?
A Setup time
B Clock polarity
C Scan ordering
D Layer density rules
Answer: D. Layer density rules. Metal fill helps meet manufacturing density requirements.
Why rerun extraction and timing after metal fill?
A RTL behavior changes
B Fill changes parasitics
C Clock frequency changes
D Cells disappear
Answer: B. Fill changes parasitics. Added metal can change coupling capacitance, so extraction and timing are checked again.
Multi-corner signoff checks designs across which variations?
A Area, phase, bandwidth
B Masks, wafers, dies
C Process, voltage, temperature
D RTL, netlist, GDS
Answer: C. Process, voltage, temperature. Multi-corner analysis evaluates timing under process, supply-voltage, and temperature corners.
How many cycles may data intentionally take on a multicycle path?
A More than one cycle
B Half a clock edge
C No clock edge
D Only reset
Answer: A. More than one cycle. A multicycle path is used when the architecture intentionally allows multiple cycles for data propagation.
Timing closure means what has been achieved?
A All cells are minimum size
B No clocks are used
C Only RTL passes
D All required paths meet constraints
Answer: D. All required paths meet constraints. Timing closure means setup and hold requirements are satisfied for the constrained design.
Clock-tree balancing primarily aims to control what?
A Photoresist thickness
B Transistor doping
C Clock arrival skew
D RTL indentation
Answer: C. Clock arrival skew. Balancing the clock network controls arrival differences across sequential elements.
IR drop is caused by current flowing through what?
A Gate oxide capacitance
B Power-grid resistance
C Scan-chain logic
D Photoresist
Answer: B. Power-grid resistance. Current through nonzero power-grid resistance creates a supply-voltage drop.
Electromigration risk rises with what interconnect condition?
A Low fan-out
B Long setup time
C Low clock activity
D High current density
Answer: D. High current density. High current density can move metal atoms and degrade or open interconnects.
Which traditional format stores final mask-layout geometry?
A GDSII
B VCD
C SDF
D RTL
Answer: A. GDSII. GDSII is a traditional database format used to represent IC layout for manufacturing.
SDF-annotated gate simulation includes what that functional RTL omits?
A Foundry wafer color
B Only logic truth tables
C Cell and net delays
D Only comments
Answer: C. Cell and net delays. SDF annotates cell and interconnect timing delays for gate-level simulation.