Difficulty: Easy & Basic
What does VLSI enable by integrating many devices on one die?
A Discrete resistor banks
B Optical fiber links
C Integrated circuits
D Analog-only boards
Answer: C. Integrated circuits. VLSI places a large number of devices on a single integrated circuit.
Which transistor pair forms a CMOS inverter?
A PMOS and NMOS
B Two NMOS devices
C Two PMOS devices
D BJT and diode
Answer: A. PMOS and NMOS. A CMOS inverter uses complementary p-channel and n-channel MOS transistors.
With a low input, a CMOS inverter produces what output?
A Low logic level
B High impedance
C Clock pulse
D High logic level
Answer: D. High logic level. A low input turns on the PMOS pull-up and raises the output.
As its input goes high, which device pulls an inverter output down?
A PMOS transistor
B NMOS transistor
C BJT transistor
D Zener diode
Answer: B. NMOS transistor. A high input turns on the NMOS pull-down path to ground.
Under ideal steady-state CMOS operation, why is static current small?
A No transistor switches
B No load capacitance
C No logic state
D No direct supply path
Answer: D. No direct supply path. In an ideal static CMOS gate, one network is off, so there is no direct VDD-to-ground path.
Switching a CMOS output charges and discharges what?
A Substrate resistance
B Clock register
C Load capacitance
D Photoresist layer
Answer: C. Load capacitance. Dynamic switching power is mainly associated with charging and discharging capacitances.
Dynamic CMOS power follows which common relation?
A Ξ±CVΒ²f
B Ξ±CVfΒ²
C C divided by V
D V divided by Ξ±f
Answer: A. Ξ±CVΒ²f. Dynamic power scales with activity, switched capacitance, voltage squared, and frequency.
If switching frequency doubles, dynamic power changes how?
A It halves
B It stays constant
C It doubles
D It quadruples
Answer: C. It doubles. With activity, capacitance, and voltage fixed, dynamic power is proportional to frequency.
What does fabrication yield measure?
A Masks per transistor
B Good dies per wafer
C Wires per metal layer
D Gates per clock
Answer: B. Good dies per wafer. Yield is the fraction of fabricated dies that meet functional requirements.
Leakage current contributes to which power category?
A Dynamic power only
B Clock power only
C Short-circuit delay
D Static power
Answer: D. Static power. Leakage consumes power even when logic is not switching.
Switching activity factor estimates what?
A Average transition activity
B Gate oxide thickness
C Metal wire length
D Clock-tree depth
Answer: A. Average transition activity. The activity factor represents how often circuit nodes switch.
High fan-out usually increases which load on a gate?
A Optical load
B Capacitive load
C Thermal resistance
D Mask density
Answer: B. Capacitive load. Each driven input adds capacitance, increasing the total load.
Propagation delay compares which events?
A Two supply rails
B Two mask layers
C Input and output transitions
D Clock and reset names
Answer: C. Input and output transitions. Propagation delay measures the time between an input change and its corresponding output change.
Setup time requires data stable when?
A After the clock edge
B Only during reset
C After data capture
D Before active clock edge
Answer: D. Before active clock edge. Setup time is the required stability interval before the capturing clock edge.
Hold time requires data stable when?
A Before the clock edge
B After active clock edge
C Only during reset
D Before synthesis
Answer: B. After active clock edge. Hold time is the required stability interval after the capturing edge.
RTL describes digital behavior at which abstraction?
A Register-transfer level
B Mask-transfer layer
C Resistor-transistor level
D Wafer-test level
Answer: A. Register-transfer level. Register-transfer-level descriptions express data movement and operations between registers.
Photolithography transfers a pattern into which coating?
A Copper heat sink
B Silicon wafer core
C Gate contact plug
D Photoresist layer
Answer: D. Photoresist layer. Light and a patterned mask expose selected regions of photoresist.
Thermal oxidation commonly grows what on silicon?
A Copper nitride
B Aluminum oxide
C Silicon dioxide
D Gallium arsenide
Answer: C. Silicon dioxide. Oxidizing silicon forms a silicon-dioxide layer.
Etching removes selected material from what?
A Clock waveform
B Wafer surface
C RTL source
D Timing report
Answer: B. Wafer surface. Etching selectively removes exposed material during fabrication.
Doping changes a semiconductor’s what?
A Carrier concentration
B Mask color
C Wire length
D Clock frequency
Answer: A. Carrier concentration. Dopants change the number and type of mobile charge carriers.
During deposition, fabrication adds what?
A Clock pulses
B Logic equations
C Thin material films
D Test vectors
Answer: C. Thin material films. Deposition forms thin layers of material on the wafer.
Silicon CMOS devices are commonly built on what?
A Glass fiber
B Copper sheet
C Ceramic mask
D Silicon wafer
Answer: D. Silicon wafer. The wafer provides the semiconductor substrate for silicon integrated circuits.
Metal layers mainly provide what between devices?
A Electrical interconnects
B Optical isolation
C Logic truth tables
D Wafer alignment
Answer: A. Electrical interconnects. Conductive metal layers route signals and power across the chip.
What physical shapes does an integrated-circuit layout specify?
A Only source code
B Physical geometries
C Only Boolean equations
D Clock frequency
Answer: B. Physical geometries. The layout specifies the physical shapes used to manufacture the chip.
Wafer dicing separates what after fabrication?
A Logic levels
B Metal atoms
C Individual dies
D Clock domains
Answer: C. Individual dies. Dicing cuts the processed wafer into separate integrated-circuit dies.