Given VDD halves and activity doubles, dynamic power changes by what factor?
A One quarter
B No change
C Twice
D One half
Answer: D. One half. Power scales as Ξ±VΒ²; doubling Ξ± and halving V gives 2Γ(1/2)Β²=1/2.
Add 0.8 ns cell delay to 0.4 ns wire delay. What is total?
A 0.4 ns
B 1.2 ns
C 0.8 ns
D 1.6 ns
Answer: B. 1.2 ns. The total path delay is the sum of cell and interconnect delay.
Upsizing one gate may slow its predecessor because it adds what?
A Input capacitance
B Clock jitter
C Mask alignment
D Substrate doping
Answer: A. Input capacitance. A larger gate is a heavier capacitive load for the stage driving its input.
At a symmetric CMOS inverter’s switching threshold, what is equal?
A VDD and ground
B Setup and hold
C Vin and Vout
D Rise and fall times
Answer: C. Vin and Vout. The switching point is commonly defined where input and output voltages are equal.
How much disturbance can a low noise margin tolerate?
A More clock skew
B More leakage
C Less added noise
D More routing congestion
Answer: C. Less added noise. A smaller noise margin leaves less room for noise before a logic value is misread.
Why can a three-input NAND have a slow pull-down?
A Parallel PMOS stack
B Single output resistor
C Clock-gated latch
D Series NMOS stack
Answer: D. Series NMOS stack. Series NMOS devices increase the pull-down resistance compared with a single device.
Widening an inverter’s PMOS mainly strengthens which transition?
A Rising output
B Falling output
C Clock capture
D Scan shifting
Answer: A. Rising output. The PMOS charges the output capacitance during a low-to-high output transition.
Setup analysis uses which data-path delay?
A Minimum path delay
B Maximum path delay
C Average path delay
D Zero path delay
Answer: B. Maximum path delay. Setup checks whether the slowest data path reaches the capture register in time.
Hold analysis uses which data-path delay?
A Maximum path delay
B Average path delay
C Clock period only
D Minimum path delay
Answer: D. Minimum path delay. Hold checks the fastest data path to ensure data does not change too soon.
Clock skew is the difference between what?
A Power rail voltages
B Gate widths
C Clock arrival times
D Mask pitches
Answer: C. Clock arrival times. Skew is the difference in clock arrival time at two sequential elements.
Long interconnect adds which effects to a path?
A Activity and bit depth
B Resistance and capacitance
C Setup and hold
D Logic and RTL
Answer: B. Resistance and capacitance. Wire resistance and capacitance contribute parasitic delay.
Poor cell placement can create what physical problem?
A Routing congestion
B Less transistor leakage
C Fewer timing paths
D Lower mask count
Answer: A. Routing congestion. Poor placement can crowd routing resources and lengthen interconnects.
Buffering a high-fan-out net can improve what?
A Wafer yield directly
B Threshold voltage
C Photoresist exposure
D Signal slew
Answer: D. Signal slew. Buffers divide a large load and can improve transition slew.
Clock gating reduces dynamic power by suppressing what?
A Leakage current only
B Mask defects
C Unneeded clock toggles
D Interconnect resistance
Answer: C. Unneeded clock toggles. Stopping an inactive block’s clock reduces unnecessary switching activity.
Power gating primarily reduces which inactive-block component?
A Leakage power
B Dynamic clock power
C Wire capacitance
D Setup time
Answer: A. Leakage power. Disconnecting the supply to an inactive block reduces leakage consumption.
What physical quantity represents a DRAM bit?
A Magnetic polarity
B Capacitor charge
C Optical phase
D Latch feedback
Answer: B. Capacitor charge. A DRAM cell represents its bit as charge stored on a capacitor.
Why does a DRAM array periodically refresh cells?
A Metal wires oxidize
B Clock trees drift
C Stored charge leaks
D Masks fade
Answer: C. Stored charge leaks. Charge gradually leaks from DRAM capacitors, so stored values must be restored.
Which feedback structure stores state in a conventional six-transistor SRAM cell?
A One resistor and capacitor
B Two transmission lines
C Three scan chains
D Cross-coupled inverters
Answer: D. Cross-coupled inverters. The cross-coupled inverters form the bistable storage element in a 6T SRAM cell.
During DRAM read, a sense amplifier detects what?
A Small bitline voltage difference
B Clock-tree skew
C Gate oxide color
D Scan-chain length
Answer: A. Small bitline voltage difference. The cell’s small charge perturbs the bitline, and a sense amplifier resolves that small voltage difference.
Low-threshold MOS devices usually have what leakage tradeoff?
A Lower switching activity
B Higher leakage current
C No gate capacitance
D Longer metal wires
Answer: B. Higher leakage current. Lower threshold voltage improves switching speed but generally increases subthreshold leakage.
What can gradually discharge a dynamic logic node?
A Clock skew
B Lithography
C Leakage current
D Scan shifting
Answer: C. Leakage current. Leakage gradually removes charge from the dynamic node.
Where is a tapered buffer chain most useful?
A A single mask
B Only DC leakage
C A zero-load net
D Very large capacitance
Answer: D. Very large capacitance. Progressively larger stages distribute the effort of driving a large capacitive load.
Shrinking a wire’s cross-section generally does what to resistance?
A Decreases resistance
B Increases resistance
C Eliminates capacitance
D Stops current
Answer: B. Increases resistance. For the same material and length, a smaller cross-section raises electrical resistance.
Why can a fast data path fail despite passing setup?
A Hold check
B DRC only
C LVS only
D Power signoff
Answer: A. Hold check. A path can meet the maximum-delay setup check yet arrive too early for the minimum-delay hold check.