For a two-input CMOS NAND, which network arrangement is correct?
A Series NMOS, parallel PMOS
B Parallel NMOS, series PMOS
C Series NMOS, series PMOS
D Parallel NMOS, parallel PMOS
Answer: A. Series NMOS, parallel PMOS. The NAND pull-down requires both inputs high, so its NMOS devices are in series; the PMOS pull-up devices are parallel.
For a two-input CMOS NOR, which arrangement implements the gate?
A Series NMOS, parallel PMOS
B Series NMOS, series PMOS
C Parallel NMOS, series PMOS
D Parallel NMOS, parallel PMOS
Answer: C. Parallel NMOS, series PMOS. The NOR pull-down devices are parallel, while both series PMOS devices are needed for a high output.
In complementary CMOS logic, the pull-up network is the dual of what?
A Clock tree
B Pull-down network
C Scan chain
D Metal stack
Answer: B. Pull-down network. Static CMOS networks use dual pull-up and pull-down structures.
When active, what level does a pull-up network drive?
A Logic low
B High impedance
C Metastability
D Logic high
Answer: D. Logic high. The pull-up path charges the output toward the positive supply.
Where does an active pull-down network drive the output?
A Logic high
B Logic low
C Clock enable
D Floating state
Answer: B. Logic low. The pull-down path discharges the output toward ground.
Precharge and evaluate phases identify which logic style?
A Dynamic logic
B Static CMOS
C Resistor logic
D Emitter-coupled logic
Answer: A. Dynamic logic. Dynamic logic uses clocked precharge and evaluation phases.
How does a dynamic logic node temporarily store its value?
A Magnetic flux
B Optical phase
C Stored charge
D Mechanical strain
Answer: C. Stored charge. The dynamic node’s capacitance stores charge representing its logic value.
Which weak feedback device helps preserve a dynamic node’s value?
A Sense resistor
B Clock divider
C Photo diode
D Keeper transistor
Answer: D. Keeper transistor. A keeper transistor compensates for charge loss on a dynamic node.
Which MOS pair forms a CMOS transmission gate?
A NMOS and PMOS
B Two NMOS devices
C Two PMOS devices
D Two bipolar devices
Answer: A. NMOS and PMOS. A transmission gate uses parallel NMOS and PMOS transistors.
Complementary controls let a transmission gate pass what?
A Only logic high
B Both logic levels
C Only logic low
D Clock edges only
Answer: B. Both logic levels. The complementary devices pass both high and low levels more effectively than a single pass transistor.
Slow CMOS input edges can briefly turn on what together?
A Two clock trees
B Two photoresists
C Two scan chains
D PMOS and NMOS
Answer: D. PMOS and NMOS. During a slow transition, both inverter devices may conduct briefly, creating short-circuit current.
What does synthesis obtain from a standard-cell library?
A Wafer lots and masks
B Only transistor photos
C Cells and timing models
D Only RTL comments
Answer: C. Cells and timing models. Libraries provide characterized cells and the models needed for implementation and timing.
Logic synthesis maps RTL into what?
A Gate-level netlist
B Wafer cross-section
C Metal-fill map
D Clock waveform
Answer: A. Gate-level netlist. Synthesis maps the RTL behavior into connected standard cells.
Functional RTL simulation usually omits what?
A Boolean behavior
B Register updates
C Input values
D Physical parasitic delays
Answer: D. Physical parasitic delays. Functional RTL simulation usually does not include extracted post-layout wire parasitics.
Which process-specific package supplies design rules and device models?
A Only test patterns
B Rules and device models
C Only clock constraints
D Only layout screenshots
Answer: B. Rules and device models. A PDK packages process-specific design rules, models, and implementation data.
Floorplanning defines the core and what else?
A Final test vectors
B Transistor threshold values
C Macro locations
D RTL comments
Answer: C. Macro locations. Floorplanning establishes the die or core region and major block locations.
Placement assigns physical locations to what?
A Only input vectors
B Only foundry rules
C Clock periods
D Standard cells
Answer: D. Standard cells. Placement positions standard cells within the floorplan.
Routing connects placed cells with what?
A Metal wires
B Photoresist films
C Boolean operators
D Clock constraints
Answer: A. Metal wires. Routing creates the physical interconnect between placed pins.
Clock-tree synthesis distributes which signal?
A Reset data
B Analog input
C Clock signal
D JTAG output
Answer: C. Clock signal. Clock-tree synthesis builds a network that delivers the clock to sequential elements.
Design rule checking compares layout geometry with what?
A RTL comments
B Manufacturing rules
C Training examples
D Clock names
Answer: B. Manufacturing rules. DRC checks physical shapes against foundry geometry requirements.
Layout-versus-schematic verification compares layout to what?
A Reference netlist
B Clock waveform
C Process schedule
D Logic truth table
Answer: A. Reference netlist. LVS checks whether the extracted layout connectivity matches the intended circuit netlist.
Parasitic extraction estimates which interconnect quantities?
A Voltage and frequency
B Setup and hold
C Area and yield
D Resistance and capacitance
Answer: D. Resistance and capacitance. PEX estimates parasitic resistance and capacitance from the physical layout.
Static timing analysis checks paths against what?
A Wafer color
B Logic labels
C Timing constraints
D Mask count
Answer: C. Timing constraints. STA evaluates path delays relative to clock and input/output constraints.
PPA is short for which design metrics?
A Polarity, phase, amplitude
B Power, performance, area
C Placement, pitch, alignment
D Process, photoresist, anneal
Answer: B. Power, performance, area. Power, performance, and area are common implementation objectives.
How is a hard macro usually delivered to a chip designer?
A Clock frequency only
B RTL comments only
C Random placement
D Physical layout
Answer: D. Physical layout. A hard macro is supplied as a predefined physical block with fixed geometry.