At 12 MHz, what reload gives a 3 ms Mode 1 delay?
A E890H
B FC18H
C C350H
D F448H
Answer: D. F448H. The timer ticks every 1 microsecond; 3,000 counts require 65,536−3,000 = F448H.
At 10 MHz, how long is a classic 8051 machine cycle?
A 1.2 microseconds
B 12 microseconds
C 1 microsecond
D 10 microseconds
Answer: A. 1.2 microseconds. A 12-clock machine cycle at 10 MHz lasts 12/10 MHz = 1.2 microseconds.
When a 50 kHz signal runs for 0.2 seconds, how many pulses arrive?
A 50,000
B 2,500
C 10,000
D 5,000
Answer: C. 10,000. Pulse count equals frequency times duration: 50,000 × 0.2 = 10,000.
At 12 MHz, what is the classic counter’s maximum input rate?
A 1 MHz
B 500 kHz
C 250 kHz
D 6 MHz
Answer: B. 500 kHz. Two machine cycles are needed to detect each falling edge, giving fosc/24.
For 100 timer ticks in Mode 2, what reload is needed?
A 9CH
B C8H
C 64H
D A0H
Answer: A. 9CH. An 8-bit timer needs 256−100 = 156 decimal, or 9CH.
At a 1 microsecond tick, what is the longest Mode 1 interval?
A 1.024 ms
B 256 ms
C 65.536 ms
D 32.768 ms
Answer: C. 65.536 ms. A 16-bit timer spans 65,536 ticks, each lasting one microsecond.
MOVC uses DPTR=3000H and A=05H. Which table address is read?
A 3006H
B 3050H
C 3000H
D 3005H
Answer: D. 3005H. MOVC A,@A+DPTR addresses the byte at DPTR plus the accumulator.
MOVX A,@DPTR runs with DPTR=4A20H. Which address is read?
A 4A00H
B 4A20H
C 204AH
D 20A4H
Answer: B. 4A20H. MOVX with @DPTR uses the full 16-bit external data address.
During external memory access, what captures P0’s low address byte?
A Timer latch
B SCON latch
C ALE-controlled latch
D PSW latch
Answer: C. ALE-controlled latch. P0 is multiplexed; ALE lets an external latch retain the low address byte.
During MOVX @R0 access, what does Port 2 retain?
A Interrupt vector
B Serial data byte
C Timer count
D Upper address page
Answer: D. Upper address page. The 8-bit address comes from R0 while P2 keeps the upper page byte.
With 4 KB internal code and EA high, where is code at 1000H fetched?
A External program memory
B Internal RAM
C Internal ROM
D SFR space
Answer: A. External program memory. The original 8051’s internal code ROM ends at 0FFFH.
With EA tied low, where does the 8051 fetch program code?
A Internal data RAM
B External code memory
C Port latches
D SFR space
Answer: B. External code memory. EA low selects external program memory.
What memory serves PC=0FFFH when EA is high?
A SFR space
B External data memory
C Port 0
D Internal code memory
Answer: D. Internal code memory. Address 0FFFH is the last byte within the original 4 KB code ROM.
EA is clear while ET0 is set. Can Timer 0 interrupt?
A Only after reset
B Only in Mode 2
C No, globally disabled
D Yes, ET0 overrides
Answer: C. No, globally disabled. EA must be set; individual enable bits cannot override a clear global enable.
At 12 MHz, how long must RST stay high?
A 12 microseconds
B At least 2 microseconds
C 1 nanosecond
D 1 microsecond
Answer: B. At least 2 microseconds. Reset must remain high for two machine cycles; each is 1 microsecond at 12 MHz.
How long does a two-machine-cycle instruction take at 12 MHz?
A 2 microseconds
B 12 microseconds
C 24 microseconds
D 1 microsecond
Answer: A. 2 microseconds. Each classic 8051 machine cycle is 1 microsecond at 12 MHz.
Which bit address maps to byte 2AH, bit 5?
A 52H
B 25H
C 55H
D 2AH
Answer: C. 55H. Bit addresses start at 00H for byte 20H: (2AH−20H)×8+5 = 55H.
In Timer 0 Mode 3, which control pair governs TH0?
A ET0 and IE0
B IT0 and IE1
C TR0 and TF0
D TR1 and TF1
Answer: D. TR1 and TF1. The split high byte TH0 uses TR1 and TF1 control bits.
When Timer 1 itself is configured for Mode 3, what happens to its count?
A It auto-reloads
B Its count is held
C It splits in half
D It becomes 16-bit
Answer: B. Its count is held. In this configuration Timer 1 is held; Timer 0 uses its control resources.
With Mode 2 serial and SMOD=1, what baud rate results at 3.6864 MHz?
A 115,200 baud
B 9,600 baud
C 230,400 baud
D 57,600 baud
Answer: A. 115,200 baud. Mode 2 baud is 2^SMOD×fosc/64; here 3,686,400/32 = 115,200.
MOVX A,@R0 uses R0=32H and P2=48H. Which address is selected?
A 48FFH
B 3248H
C 0032H
D 4832H
Answer: D. 4832H. R0 supplies the low byte and P2 supplies the high page byte.
What value does the 8051 place in P0’s latch during external access?
A 7FH
B 00H
C FFH
D 80H
Answer: C. FFH. External memory cycles automatically write FFH to the Port 0 latch.
Which signals distinguish external code reads from data reads?
A PSEN versus RD/WR
B EA versus INT0
C ALE versus RST
D TXD versus RXD
Answer: A. PSEN versus RD/WR. External code uses PSEN; external data transfers use RD and WR.
With direct addressing, what is the source in MOV A,30H?
A Port 3 pins
B Byte at address 30H
C DPTR value
D Constant 30H
Answer: B. Byte at address 30H. Without #, 30H is a direct internal data address.
What does # mark in MOV A,#30H?
A Port 3 pins
B DPTR value
C Byte at address 30H
D Constant 30H
Answer: D. Constant 30H. The # marks an immediate constant rather than a memory address.