For a standalone sensor controller, which device combines processing and peripherals?
A FPGA
B Microcontroller
C Transceiver
D Microprocessor
Answer: B. Microcontroller. Microcontrollers integrate the CPU and common peripherals, fitting compact embedded control.
What is the classic 8051 data width?
A 16-bit
B 32-bit
C 4-bit
D 8-bit
Answer: D. 8-bit. The original 8051 has an 8-bit CPU and data path.
How wide is the 8051 program counter?
A 16-bit
B 12-bit
C 32-bit
D 8-bit
Answer: A. 16-bit. Its 16-bit program counter addresses a 64 KB code space.
How much on-chip ROM came with the original 8051?
A 2 KB
B 128 bytes
C 4 KB
D 8 KB
Answer: C. 4 KB. The original Intel 8051 included 4 KB of on-chip program ROM.
How much internal RAM does the original 8051 provide?
A 128 bytes
B 256 bytes
C 1 KB
D 32 bytes
Answer: A. 128 bytes. The base 8051 has 128 bytes of internal data RAM.
How many parallel ports are named P0 through P3?
A Eight
B Three
C Two
D Four
Answer: D. Four. Ports P0, P1, P2, and P3 make four 8-bit ports.
How many digital I/O pins do those ports provide?
A 40 pins
B 32 pins
C 24 pins
D 16 pins
Answer: B. 32 pins. Four 8-bit ports provide 32 I/O pins.
What does DPTR provide to 8051 programs?
A Status flags
B 8-bit counter
C 16-bit data pointer
D Serial buffer
Answer: C. 16-bit data pointer. The 16-bit DPTR is used as a data pointer.
Which register is the main arithmetic accumulator?
A Register SP
B Register B
C Register R0
D Register A
Answer: D. Register A. The 8051 accumulator is register A, also called ACC.
Which register identifies the next code address?
A Data pointer
B Program counter
C Status word
D Stack pointer
Answer: B. Program counter. The program counter holds the address for the next instruction fetch.
What does PSW primarily hold?
A Status flags
B Port values
C Code bytes
D Timer reloads
Answer: A. Status flags. The Processor Status Word contains flags and register-bank selection bits.
Which architecture separates code and data spaces?
A Ring
B Von Neumann
C Harvard
D Stack
Answer: C. Harvard. The 8051 uses separate program and data memory spaces.
How many timer/counter units exist in the base 8051?
A One
B Two
C Three
D Four
Answer: B. Two. The base 8051 provides Timer 0 and Timer 1.
What is the width of each base 8051 timer/counter?
A 16-bit
B 13-bit
C 8-bit
D 32-bit
Answer: A. 16-bit. Timer 0 and Timer 1 are each 16-bit units.
Which serial capability is built into the 8051?
A Receive only
B Transmit only
C Half duplex
D Full duplex
Answer: D. Full duplex. The 8051 serial port can transmit and receive simultaneously.
Where are 8051 special function registers mapped?
A 20H–2FH
B 00H–1FH
C 80H–FFH
D 30H–7FH
Answer: C. 80H–FFH. SFRs occupy the upper address range, 80H through FFH.
How many selectable register banks are provided?
A Two
B Four
C Eight
D Three
Answer: B. Four. Two PSW bits select one of four register banks.
How many registers are in each register bank?
A Six
B Four
C Sixteen
D Eight
Answer: D. Eight. Each bank contains R0 through R7.
How large is the bit-addressable internal RAM area?
A 16 bytes
B 64 bytes
C 32 bytes
D 8 bytes
Answer: A. 16 bytes. Internal RAM locations 20H through 2FH form a 16-byte bit-addressable area.
How many individual bits fit in that RAM area?
A 256 bits
B 64 bits
C 128 bits
D 16 bits
Answer: C. 128 bits. Sixteen bytes contain 128 individually addressable bits.
Where does program execution begin after reset?
A 0023H
B 0000H
C 000BH
D 0003H
Answer: B. 0000H. The program counter is reset to 0000H.
What value does the stack pointer take after reset?
A 07H
B 20H
C 00H
D FFH
Answer: A. 07H. The original 8051 reset value for SP is 07H.
What value appears in port latches after reset?
A 07H
B 00H
C 80H
D FFH
Answer: D. FFH. The reset state sets the P0–P3 latches to FFH.
What code-space capacity follows from a 16-bit address?
A 4 KB
B 16 KB
C 64 KB
D 128 KB
Answer: C. 64 KB. Sixteen address bits represent 65,536 byte locations.
Which PSW bits select the register bank?
A EA and ET0
B RS1 and RS0
C CY and AC
D OV and P
Answer: B. RS1 and RS0. RS1 and RS0 choose the active register bank.