At 12 MHz, how long is one classic 8051 machine cycle?
A 12 microseconds
B 12 nanoseconds
C 1 microsecond
D 1 millisecond
Answer: C. 1 microsecond. A classic 12-clock 8051 uses 12 oscillator periods per machine cycle.
In timer mode, what advances Timer 0 or Timer 1?
A Port changes
B Machine cycles
C Interrupt vectors
D Serial frames
Answer: B. Machine cycles. In timer mode, the count increments once per machine cycle.
In counter mode, which input transition increments the count?
A Either edge
B No transition
C Low to high
D High to low
Answer: D. High to low. The classic 8051 counter detects a high-to-low transition on T0 or T1.
Which register selects timer operating modes?
A TMOD
B IP
C IE
D TCON
Answer: A. TMOD. TMOD contains the mode-select and timer/counter control bits.
Which register contains TR0 and TF0?
A SCON
B PSW
C TCON
D TMOD
Answer: C. TCON. TCON includes timer run controls and overflow flags.
What is the timer width in Mode 0?
A 13-bit
B 16-bit
C 8-bit
D 24-bit
Answer: A. 13-bit. Mode 0 uses a 13-bit timer/counter arrangement.
What is the timer width in Mode 1?
A 8-bit
B 16-bit
C 24-bit
D 13-bit
Answer: B. 16-bit. Mode 1 uses the full 16-bit timer/counter.
What does Timer Mode 2 provide?
A 13-bit capture
B 16-bit compare
C 32-bit cascade
D 8-bit auto-reload
Answer: D. 8-bit auto-reload. Mode 2 counts in TLx and reloads it from THx after overflow.
Which timer is split into TL0 and TH0 in Mode 3?
A Timer 0
B Timer 1
C Both timers
D Neither timer
Answer: A. Timer 0. Mode 3 divides Timer 0 into two separate 8-bit counters.
Which bit starts Timer 0 running?
A IT0
B TF0
C TR0
D IE0
Answer: C. TR0. Setting TR0 in TCON starts Timer 0.
Which bit records Timer 0 overflow?
A TF1
B TF0
C TR0
D IE0
Answer: B. TF0. TF0 is set when Timer 0 rolls over.
With GATE0 set, what else must be high?
A ALE pin
B RxD pin
C RST pin
D INT0 pin
Answer: D. INT0 pin. With GATE0 enabled, Timer 0 runs only while INT0 is high and TR0 is set.
How many vectored interrupt sources are in the base 8051?
A Four
B Three
C Five
D Six
Answer: C. Five. The base 8051 provides two external, two timer, and one serial interrupt.
Where is the INT0 interrupt vector?
A 0003H
B 0000H
C 000BH
D 0013H
Answer: A. 0003H. The external interrupt 0 service vector is 0003H.
Where is the Timer 0 interrupt vector?
A 0003H
B 000BH
C 0013H
D 001BH
Answer: B. 000BH. Timer 0 uses vector address 000BH.
Where is the Timer 1 interrupt vector?
A 000BH
B 0023H
C 0013H
D 001BH
Answer: D. 001BH. Timer 1 uses vector address 001BH.
Where is the serial interrupt vector?
A 0023H
B 0030H
C 0013H
D 001BH
Answer: A. 0023H. The serial interrupt vector is 0023H.
Which IE bit enables Timer 1 interrupts?
A ET0
B EX1
C ET1
D ES
Answer: C. ET1. ET1 is the Timer 1 interrupt-enable bit.
When IT0 equals one, INT0 is triggered by what?
A Rising edge
B Low level
C High level
D Falling edge
Answer: D. Falling edge. IT0=1 selects edge-triggered operation, responding to a falling edge.
Which register sets interrupt priority levels?
A TCON
B IP
C IE
D TMOD
Answer: B. IP. The IP register assigns high or low priority to interrupt sources.
What can a high-priority interrupt do during a low-priority ISR?
A Replace its vector
B Disable its clock
C Preempt it
D Clear its code
Answer: C. Preempt it. A high-priority interrupt may interrupt a lower-priority ISR.
What does hardware save when entering an ISR?
A Program counter
B Timer mode
C Serial mode
D Port latch
Answer: A. Program counter. Interrupt entry pushes the interrupted program counter onto the stack.
Which instruction returns from an interrupt service routine?
A RETI only clears
B JMP
C RET
D RETI
Answer: D. RETI. RETI restores the return address and signals the end of interrupt service.
Why can 8051 serial transmit and receive concurrently?
A Shared timer
B Separate SBUF registers
C Two CPUs
D Dual program counters
Answer: B. Separate SBUF registers. Transmit and receive use physically separate SBUF registers at the same address.
Which flags share the serial interrupt vector?
A RI and TI
B TF0 and TF1
C CY and AC
D IE0 and IE1
Answer: A. RI and TI. Receive and transmit flags both request service through vector 0023H.