In plain GPIO use without alternate functions, which classic 8051 port is the natural choice?
A Port 1
B Port 2
C Port 0
D Port 3
Answer: A. Port 1. Port 1 has no alternate peripheral function on the classic 8051.
During external-memory cycles, which port multiplexes the low address and data?
A Port 2
B Port 3
C Port 0
D Port 1
Answer: C. Port 0. P0 carries the low address byte and data during external memory cycles.
Where does the high address byte appear during 16-bit external access?
A Port 1
B Port 2
C Port 0
D Port 3
Answer: B. Port 2. P2 supplies the high address byte for 16-bit external memory access.
Which port multiplexes serial, timer, and interrupt functions?
A Port 2
B Port 0
C Port 1
D Port 3
Answer: D. Port 3. P3 pins include serial, interrupt, timer, and memory-control functions.
Where does serial receive data enter the 8051?
A P3.1
B P3.2
C P3.3
D P3.0
Answer: D. P3.0. P3.0 is the alternate-function pin for RxD.
Where does serial transmit data leave the 8051?
A P3.5
B P3.1
C P3.4
D P3.0
Answer: B. P3.1. P3.1 is the alternate-function pin for TxD.
INT0 is assigned to which P3 pin?
A P3.0
B P3.3
C P3.2
D P3.1
Answer: C. P3.2. INT0 is multiplexed onto P3.2.
On which P3 pin is INT1 found?
A P3.3
B P3.4
C P3.2
D P3.1
Answer: A. P3.3. INT1 is multiplexed onto P3.3.
Which P3 input accepts Timer 0 counter pulses?
A P3.5
B P3.4
C P3.2
D P3.3
Answer: B. P3.4. The T0 input is the alternate function of P3.4.
Where does Timer 1 receive external counter pulses?
A P3.4
B P3.6
C P3.3
D P3.5
Answer: D. P3.5. The T1 input is the alternate function of P3.5.
Which pin carries /WR during an external data write?
A P3.7
B P3.5
C P3.6
D P3.4
Answer: C. P3.6. P3.6 carries the external-memory /WR signal.
How is /RD exposed for an external memory read?
A P3.7
B P3.3
C P3.5
D P3.6
Answer: A. P3.7. P3.7 carries the external-memory /RD signal.
What does Port 0 need for a GPIO high output?
A Current mirror
B Internal pull-up
C Series capacitor
D External pull-up
Answer: D. External pull-up. P0 is open drain in GPIO use, so an external pull-up creates a high level.
What should software write before reading a quasi-bidirectional input?
A Logic zero
B Logic one
C Carry flag
D Timer reload
Answer: B. Logic one. Writing 1 releases the port pin so an external source can drive it.
Which register configures serial-port operation?
A SCON
B TCON
C PCON
D TMOD
Answer: A. SCON. SCON holds serial mode and control bits.
Which register holds the byte transferred over the serial port?
A DPTR
B SCON
C SBUF
D PSW
Answer: C. SBUF. Software writes transmit data to SBUF and reads received data there.
Which SCON bit enables serial reception?
A SM2
B RB8
C TB8
D REN
Answer: D. REN. REN is the receiver-enable bit in SCON.
Which flag indicates a received serial byte?
A TF0
B RI
C TI
D IE0
Answer: B. RI. RI is set when a serial byte is received.
Which flag indicates serial transmission completion?
A TI
B TF1
C RI
D IE1
Answer: A. TI. TI signals that the transmit buffer has completed sending.
Which register enables interrupt sources?
A IP
B SCON
C IE
D TMOD
Answer: C. IE. IE contains individual interrupt enables and the global EA bit.
Which IE bit globally enables interrupts?
A ET0
B EA
C ES
D EX1
Answer: B. EA. EA is the global interrupt-enable bit.
Which signal strobes an external code-memory read?
A RD
B ALE
C WR
D PSEN
Answer: D. PSEN. PSEN is the program-store enable read strobe for external code.
Which pin selects internal versus external code memory?
A ALE
B RST
C EA
D PSEN
Answer: C. EA. EA selects the use of internal program memory when available.
Which instruction family accesses external data memory?
A MOVX
B XCH
C MOVC
D MOV
Answer: A. MOVX. MOVX instructions transfer data to or from external data memory.
Which instruction reads a code-memory lookup table?
A MOVX
B MOVC
C MOV
D XCH
Answer: B. MOVC. MOVC reads a byte from program/code memory.