Flynn’s taxonomy classifies computers by instruction and what streams?
A Data streams
B Power streams
C Clock sources
D Memory pages
Answer: A. Data streams. Flynn’s taxonomy uses instruction-stream and data-stream counts.
SISD means single instruction and what data stream?
A Shared data
B Single data
C Serial data
D Multiple data
Answer: B. Single data. SISD executes one instruction stream on one data stream.
SIMD uses one instruction stream across what?
A One data item
B Multiple data
C Multiple instruction streams
D No data stream
Answer: B. Multiple data. SIMD applies one operation to multiple data elements.
MIMD uses multiple instructions and what data?
A Single data only
B No data
C Multiple data
D Shared instruction only
Answer: C. Multiple data. MIMD processors run independent instruction streams on different data.
NUMA memory access time depends partly on what?
A Instruction opcode
B Memory location
C Screen resolution
D File name
Answer: B. Memory location. In NUMA systems, local memory access is usually faster than remote memory.
An interconnect links processors, memory and what?
A I/O devices
B Only software licenses
C Only cooling fans
D Display colors
Answer: A. I/O devices. Interconnects carry communication among system components.
Instruction-level parallelism executes independent instructions what?
A Only sequentially
B After reboot
C On disk only
D Concurrently
Answer: D. Concurrently. ILP exploits independent operations within a single instruction stream.
Throughput measures completed work per what?
A Instruction length
B Memory size
C Unit time
D Power voltage
Answer: C. Unit time. Throughput is the rate of completed operations or tasks.
Latency measures time to complete what?
A All system work
B A memory capacity
C A clock frequency
D One operation
Answer: D. One operation. Latency is elapsed time for an individual operation or response.
Processor performance improves with lower CPI or what clock property?
A Larger register names
B More file formats
C Lower bus width always
D Higher clock rate
Answer: D. Higher clock rate. CPU execution time depends on instruction count, CPI and clock period.
A cache-coherence protocol handles shared data across what?
A Separate files
B Power supplies
C Network switches only
D Processor caches
Answer: D. Processor caches. Coherence protocols coordinate cached copies in multiprocessor systems.
A MESI line in Modified state is what?
A Shared and clean
B Dirty and exclusive
C Invalid
D Uncached only
Answer: B. Dirty and exclusive. Modified indicates a unique cache copy changed from memory.
A dirty cache line must be written back before what?
A Every read
B Every clock
C Eviction
D Any arithmetic operation
Answer: C. Eviction. Dirty data must be propagated to lower memory when replaced.
A write-invalidate protocol sends what to other caches?
A Data copy always
B Clock pulse
C Power reset
D Invalidation message
Answer: D. Invalidation message. Write-invalidate coherence clears other cached copies before a write.
Cache false sharing can cause unnecessary what?
A Instruction decode
B Power conversion
C Coherence traffic
D Address translation only
Answer: C. Coherence traffic. Independent variables sharing a line can trigger avoidable coherence transfers.
A GPU is designed for high data-parallel what?
A Serial latency only
B Single-thread branch depth
C Throughput
D Disk storage
Answer: C. Throughput. GPUs use many processing units for parallel workloads.
Power management may reduce clock frequency through what?
A Dynamic scaling
B Cache mirroring
C Address decoding
D Parity generation
Answer: A. Dynamic scaling. Dynamic frequency scaling lowers performance and power when demand is low.
Thermal throttling reduces performance to control what?
A Memory capacity
B Address width
C Temperature
D Instruction count
Answer: C. Temperature. Processors lower frequency or voltage to remain within thermal limits.
Reliability, availability and serviceability are abbreviated how?
A RAS
B SIMD
C DMA
D CPI
Answer: A. RAS. RAS features support fault detection, recovery and serviceability.
ECC can correct what type of memory error?
A Single-bit error
B Any multi-bit error always
C Cache miss
D Address translation
Answer: A. Single-bit error. Many ECC schemes correct single-bit errors and detect some multi-bit errors.
A performance benchmark measures system behavior under what?
A No workload
B Specified workload
C Only power-off
D Unknown hardware
Answer: B. Specified workload. Benchmarks compare performance using defined tasks and conditions.
Amdahl’s speedup approaches a limit set by what?
A Serial fraction
B Cache associativity
C Word size
D Bus encoding
Answer: A. Serial fraction. The serial portion limits maximum parallel speedup.
Superscalar issue width counts instructions dispatched per what?
A Memory page
B Clock cycle
C Cache line
D Second only
Answer: B. Clock cycle. Issue width is the maximum instructions dispatched in one cycle.
A branch misprediction causes what pipeline effect?
A More memory capacity
B Higher cache hit
C No latency
D Flushed work
Answer: D. Flushed work. Wrong-path instructions are discarded and the pipeline restarts.
A load-store architecture performs memory access using what instructions?
A Load and store
B Every arithmetic instruction
C Branch only
D Cache flush
Answer: A. Load and store. Load-store designs use dedicated instructions to move data between memory and registers.