DRAM stores bits using capacitor charge and what access device?
A Magnetic head
B Transistor
C Laser diode
D Relay coil
Answer: B. Transistor. A DRAM cell typically uses a capacitor and access transistor.
SRAM stores bits using what circuit structure?
A Bistable latch
B Capacitor only
C Magnetic domain
D Optical mark
Answer: A. Bistable latch. SRAM uses cross-coupled transistors to retain state while powered.
DRAM requires periodic what to retain data?
A Reformatting
B Rebooting
C Cooling only
D Refresh
Answer: D. Refresh. DRAM capacitors leak charge, so memory cells must be refreshed.
SDRAM synchronizes commands with what?
A System clock
B Power waveform
C Printer timing
D Network address
Answer: A. System clock. Synchronous DRAM operates in step with a clock.
DDR memory transfers data on what clock edges?
A Rising edge only
B Falling edge only
C Both edges
D No clock edge
Answer: C. Both edges. Double data rate transfers on both rising and falling edges.
ECC memory adds redundant bits to detect or correct what?
A Memory errors
B Cache misses
C Clock drift
D Address aliases only
Answer: A. Memory errors. Error-correcting code stores check bits with data.
Flash memory is what type of storage?
A Volatile register
B Magnetic tape
C Nonvolatile semiconductor
D Optical disc only
Answer: C. Nonvolatile semiconductor. Flash retains data without power and can be electrically erased.
Memory interleaving improves bandwidth using what?
A One slower bank
B Multiple banks
C Single register
D Larger opcode
Answer: B. Multiple banks. Interleaving overlaps accesses across independent memory banks.
Memory-mapped I/O assigns devices what?
A Cache policies
B Instruction opcodes
C Address-space locations
D Clock domains
Answer: C. Address-space locations. Memory-mapped devices are accessed with loads and stores to assigned addresses.
Isolated I/O uses what separate space?
A I/O address space
B Cache space
C Stack space
D Program counter space
Answer: A. I/O address space. Port-mapped I/O uses a separate address space and special instructions.
DMA transfers data between a device and what?
A ALU only
B Main memory
C Printer paper
D Cache tag only
Answer: B. Main memory. DMA moves bulk data without continuous CPU copying.
An interrupt vector identifies what handler?
A Cache line
B Memory bank
C Service routine
D Power state
Answer: C. Service routine. An interrupt vector points to the corresponding interrupt service routine.
Polling differs from interrupts because the CPU does what?
A Waits for event signal
B Transfers via DMA only
C Disables all I/O
D Checks device repeatedly
Answer: D. Checks device repeatedly. Polling uses repeated status checks by the processor.
Bus arbitration allocates a shared bus among what?
A Memory pages
B Requesting masters
C Cache tags
D Clock cycles only
Answer: B. Requesting masters. Arbitration selects which bus master may use a shared interconnect.
PCI Express transfers data using what signaling style?
A Serial point-to-point links
B Shared parallel bus only
C Optical discs
D Hydraulic channels
Answer: A. Serial point-to-point links. PCIe uses high-speed serial point-to-point lanes.
A PCIe lane includes transmit and what differential pair?
A Receive
B Clock divider
C Address line
D Power rail only
Answer: A. Receive. Each lane has transmit and receive differential signaling.
NVMe is a storage protocol designed for what interface?
A PCI Express
B Parallel printer port
C IDE only
D Optical SATA only
Answer: A. PCI Express. NVMe accesses nonvolatile storage over PCIe.
RAID 1 provides data redundancy through what?
A Striping only
B Mirroring
C Parity only
D Compression
Answer: B. Mirroring. RAID 1 stores duplicate copies across drives.
RAID 0 improves performance using what?
A Mirroring
B Parity only
C Error correction
D Striping
Answer: D. Striping. RAID 0 distributes data across drives but provides no redundancy.
RAID 5 combines striping with distributed what?
A Mirroring only
B Compression
C Parity
D Encryption only
Answer: C. Parity. RAID 5 stores distributed parity to tolerate one drive failure.
Big-endian storage places most significant byte at what address?
A Highest address
B Middle address
C A separate page
D Lowest address
Answer: D. Lowest address. Big-endian ordering stores the most significant byte first at the lowest address.
A storage controller manages requests to what devices?
A CPU registers only
B ALU flags
C Display pixels
D Persistent storage
Answer: D. Persistent storage. Storage controllers coordinate transfers to drives or flash devices.
A page fault occurs when a virtual page is not in what?
A Instruction register
B Cache only
C I/O port
D Physical memory
Answer: D. Physical memory. A page fault signals that a referenced virtual page is not currently resident.
A TLB caches virtual-to-physical what?
A Data bytes
B Instruction opcodes
C Address translations
D Disk blocks only
Answer: C. Address translations. The TLB stores recently used address mappings.
A cache line is transferred between cache and what?
A Keyboard
B Lower memory level
C CPU control unit
D Power supply
Answer: B. Lower memory level. Caches move data in fixed-size blocks called lines or cache blocks.