An instruction set architecture defines what software-visible interface?
A Only cache replacement
B Only machine dimensions
C Printer protocols
D Processor instructions and state
Answer: D. Processor instructions and state. The ISA specifies instructions, registers, data types and behavior visible to software.
Microarchitecture describes how an ISA is what?
A Translated into Unicode
B Stored on disk
C Printed on paper
D Implemented in hardware
Answer: D. Implemented in hardware. Microarchitecture is the internal hardware design that implements an ISA.
A RISC design generally favors what instruction style?
A Very complex instructions only
B No registers
C Variable analog operations
D Simple regular instructions
Answer: D. Simple regular instructions. RISC designs commonly use simpler instructions and load-store organization.
A CISC design commonly provides what instruction characteristic?
A No addressing modes
B Complex instruction set
C Only one instruction
D Fixed analog instructions
Answer: B. Complex instruction set. CISC architectures may include more complex instructions and addressing modes.
The opcode identifies what part of an instruction?
A Operation to perform
B Operand value only
C Memory size
D Clock frequency
Answer: A. Operation to perform. The opcode specifies the operation such as add, load or branch.
An instruction operand identifies what?
A Data or location
B Operation code
C Clock edge
D Power rail
Answer: A. Data or location. Operands are values, registers or addresses used by an instruction.
Immediate addressing stores operand value where?
A Inside instruction
B In a memory pointer only
C In cache tag
D In I/O port always
Answer: A. Inside instruction. Immediate mode encodes the constant within the instruction.
Register addressing obtains an operand from what?
A CPU register
B Main memory only
C Disk sector
D Network packet
Answer: A. CPU register. Register addressing names a processor register as the operand source.
Indirect addressing uses an address stored where?
A In the opcode only
B In an ALU flag
C In a cache line only
D In another location
Answer: D. In another location. Indirect mode fetches the effective address from a register or memory location.
Indexed addressing combines a base address with what?
A Opcode length
B Index value
C Clock period
D Cache line state
Answer: B. Index value. Indexed addressing adds an index register to a base address.
The program counter stores the address of what?
A Last output value
B Next instruction
C Current cache line
D Stack contents only
Answer: B. Next instruction. The program counter tracks the next instruction to fetch.
The instruction register contains what?
A Next data byte
B Current instruction
C Stack pointer
D Cache index only
Answer: B. Current instruction. The instruction register holds the fetched instruction being processed.
A register file provides what to the execution unit?
A Long-term file storage
B Network routing
C Fast operand storage
D Cooling control
Answer: C. Fast operand storage. A register file is a bank of fast CPU registers.
The stack pointer identifies what?
A Next instruction
B Cache tag
C Top of stack
D I/O device only
Answer: C. Top of stack. The stack pointer points to the current top of the stack.
Status flags record conditions such as zero and what?
A Carry
B Cache size
C Memory type
D Clock source
Answer: A. Carry. Condition codes include zero, carry, sign and overflow flags.
The memory hierarchy orders storage by speed, cost and what?
A Color depth
B Instruction syntax
C Network protocol
D Capacity
Answer: D. Capacity. Memory levels trade off latency, cost per bit and capacity.
Temporal locality means recent data is likely to be used when?
A Never again
B Again soon
C Only after reboot
D At a lower address
Answer: B. Again soon. Temporal locality predicts reuse of recently accessed data.
Direct-mapped cache assigns each memory block to what?
A Any cache line
B Every cache line
C Main memory only
D One cache line
Answer: D. One cache line. Each block has exactly one possible line based on its index.
Fully associative cache allows a block in what location?
A Any cache line
B One fixed line
C No cache line
D Only first line
Answer: A. Any cache line. A fully associative cache permits any memory block in any line.
Set-associative cache maps a block to one set and what?
A Any way in set
B Any set and way
C One fixed way globally
D Main memory only
Answer: A. Any way in set. A block maps to a set and can occupy any way in that set.
Write-through cache updates cache and what on each write?
A Disk only
B TLB only
C Main memory
D Register file only
Answer: C. Main memory. Write-through sends each store to both cache and lower memory.
Write-back cache delays main-memory update until what?
A Every read
B Every clock cycle
C Line eviction
D Power-up only
Answer: C. Line eviction. Dirty data is written back when its cache line is evicted.
LRU replacement evicts the line used what?
A Most recently
B Most frequently only
C Least recently
D At random always
Answer: C. Least recently. Least-recently-used policy removes the line with the oldest recent access.
Cache hit ratio is hits divided by what?
A Misses only
B Cache lines
C Total accesses
D Memory capacity
Answer: C. Total accesses. Hit ratio measures the fraction of accesses served by the cache.
AMAT includes hit time plus miss rate times what?
A Cache capacity
B Miss penalty
C Address width
D Clock count only
Answer: B. Miss penalty. Average memory access time is hit time plus miss rate multiplied by miss penalty.