The fetch stage reads an instruction from what?
A Output device
B Power supply
C Instruction memory
D Cooling fan
Answer: C. Instruction memory. Instruction fetch obtains the next instruction from memory or cache.
The decode stage interprets opcode and what?
A Cache temperature
B Machine serial number
C Operands
D Power budget
Answer: C. Operands. Decode identifies the operation and operand requirements.
A hardwired control unit generates signals using what?
A Stored microinstructions only
B User documents
C Logic circuits
D Network packets
Answer: C. Logic circuits. Hardwired control uses combinational and sequential logic to generate control signals.
A microprogrammed controller stores control sequences in what?
A Data cache only
B Register file
C I/O port
D Control memory
Answer: D. Control memory. Microinstructions in control memory generate processor control signals.
CPI is average cycles per what?
A Memory byte
B Cache line
C Clock second
D Instruction
Answer: D. Instruction. CPI is the average number of clock cycles per instruction.
A pipeline increases instruction throughput by overlapping what?
A Memory banks only
B Clock sources
C Instruction stages
D Power rails
Answer: C. Instruction stages. Pipelining overlaps stages of different instructions.
A structural hazard occurs when instructions compete for what?
A Same hardware resource
B Different data values
C Branch target
D Register name only
Answer: A. Same hardware resource. Structural hazards arise when hardware cannot serve simultaneous operations.
A data hazard occurs when an instruction depends on what?
A Later cache line
B Power state
C Earlier result
D Instruction length only
Answer: C. Earlier result. Data hazards occur when operations have read-after-write or related dependencies.
A control hazard is often caused by what instruction?
A Add operation
B Load only
C Cache flush only
D Branch
Answer: D. Branch. Branches change instruction flow and may delay fetch decisions.
Forwarding reduces stalls by sending results from what?
A Disk to memory
B Printer to CPU
C Pipeline stage to stage
D Clock to cache only
Answer: C. Pipeline stage to stage. Bypassing forwards a result directly to a dependent stage.
A pipeline stall inserts what into execution?
A New register
B Cache line
C Instruction opcode
D Idle cycle or bubble
Answer: D. Idle cycle or bubble. A stall delays an instruction, often inserting a bubble.
Branch prediction estimates what before branch resolves?
A Branch outcome
B Cache capacity
C ALU result only
D Power draw
Answer: A. Branch outcome. Prediction guesses the next control-flow path to keep the pipeline busy.
A superscalar processor can issue multiple instructions in what?
A One second only
B One cycle
C One cache line
D One program only
Answer: B. One cycle. Superscalar execution dispatches multiple instructions per clock cycle.
VLIW encodes multiple operations into what?
A Wide instruction word
B Cache tag
C Memory page
D Clock divider
Answer: A. Wide instruction word. Very long instruction word formats bundle operations for parallel execution.
Out-of-order execution allows independent instructions to execute how?
A Only in source order
B After program end
C Without operands
D Before older stalled ones
Answer: D. Before older stalled ones. Out-of-order cores execute ready instructions while preserving architectural results.
Register renaming removes false dependencies on what?
A Architectural registers
B Memory addresses
C Cache lines
D Clock signals
Answer: A. Architectural registers. Renaming maps architectural registers to physical registers to avoid name hazards.
Speculative execution performs work before what is certain?
A Instruction decode
B Branch outcome
C Clock edge
D Power supply
Answer: B. Branch outcome. Speculation executes predicted-path instructions before confirming control flow.
SIMD applies one instruction to what data pattern?
A One serial bit
B Multiple data elements
C Multiple programs only
D One cache tag
Answer: B. Multiple data elements. SIMD performs the same operation across multiple data items.
Vector processing operates on what data structure?
A Only scalar values
B Instruction addresses
C Bus control bits
D Data vectors
Answer: D. Data vectors. Vector units apply operations to arrays of elements.
Cache coherence maintains agreement among what?
A Cached memory copies
B Clock domains
C Instruction formats
D Power supplies
Answer: A. Cached memory copies. Coherence protocols keep shared data consistent across caches.
MESI names Modified, Exclusive, Shared and what state?
A Invalid
B Idle
C Indexed
D Interrupted
Answer: A. Invalid. MESI is a cache-coherence protocol with four named line states.
False sharing occurs when threads modify different data in what?
A Different processors only
B Same cache line
C Different files
D Separate pages always
Answer: B. Same cache line. Coherence traffic can occur when independent variables share a cache line.
A multicore processor contains multiple what?
A Power grids
B CPU cores
C I/O buses only
D Operating systems only
Answer: B. CPU cores. Multiple cores execute instructions within one processor package.
SMT allows one core to expose multiple what?
A Physical caches only
B Hardware threads
C Power supplies
D Instruction sets
Answer: B. Hardware threads. Simultaneous multithreading lets one core manage multiple hardware thread contexts.
Amdahl’s law limits speedup due to what?
A Serial work fraction
B Cache size only
C Bus voltage
D Clock label
Answer: A. Serial work fraction. Nonparallelizable portions limit total system speedup.