Address decoding selects which memory or I/O device?
A Clock source
B Data value
C Stack order
D Targeted address range
Answer: D. Targeted address range. Address decoders activate a device when its address range is selected.
A latch can separate multiplexed address from what bus?
A Power bus
B Data bus
C Clock bus
D Interrupt bus
Answer: B. Data bus. An external latch holds the address while shared pins carry data.
A memory interface coordinates processor with what?
A Memory chips
B Cooling fan
C Monitor
D Power cable only
Answer: A. Memory chips. Memory interfacing connects address, data and control signals to memory devices.
Memory-mapped I/O uses which address space?
A Memory address space
B Separate port space
C Only stack space
D Only instruction cache
Answer: A. Memory address space. Memory-mapped devices appear in the normal memory address map.
Isolated I/O uses what separate addressing?
A I/O port space
B Virtual pages
C Cache set space
D Stack addresses only
Answer: A. I/O port space. Isolated I/O uses a distinct I/O address space and instructions.
The 8255 is a programmable what?
A Interrupt controller
B DMA controller
C Peripheral interface
D Timer only
Answer: C. Peripheral interface. The 8255 programmable peripheral interface provides configurable digital I/O ports.
The 8253 programmable device provides what function?
A Serial interface
B DMA transfer
C Timer and counter
D ADC conversion
Answer: C. Timer and counter. The 8253 contains programmable interval timers and counters.
The 8259 manages what processor requests?
A Memory refresh
B Serial data
C Interrupt requests
D Analog voltage
Answer: C. Interrupt requests. The 8259 programmable interrupt controller prioritizes and manages interrupts.
The 8251 is a programmable what interface?
A Parallel port only
B Serial communication
C Timer counter
D DMA channel
Answer: B. Serial communication. The 8251 USART handles synchronous and asynchronous serial communication.
The 8237 is associated with what function?
A DMA control
B Interrupt priority
C Serial I/O
D Timer output
Answer: A. DMA control. The 8237 DMA controller manages direct memory access transfers.
An ADC converts analog voltage into what?
A Digital code
B Mechanical motion
C Serial clock only
D Hydraulic pressure
Answer: A. Digital code. An analog-to-digital converter samples and quantizes analog input.
A DAC converts digital code into what?
A Memory address
B Interrupt request
C Clock edge
D Analog output
Answer: D. Analog output. A digital-to-analog converter generates a corresponding analog signal.
An address decoder can use upper address bits to select what?
A Data parity
B Clock phase
C Accumulator value
D Chip enable
Answer: D. Chip enable. Upper address bits are decoded to select a memory or peripheral chip.
A wait state extends time for what slower component?
A Bus transaction
B Instruction width
C Address range
D Clock frequency permanently
Answer: A. Bus transaction. Wait states allow slower memory or peripherals to meet timing.
READY input can signal when a peripheral is what?
A Out of address space
B Reset permanently
C In DMA only
D Prepared for transfer
Answer: D. Prepared for transfer. READY indicates whether an external device can complete the bus transfer.
DMA allows data transfer with reduced what?
A Memory capacity
B Bus width
C CPU involvement
D Interrupt priority
Answer: C. CPU involvement. DMA transfers data without continuous processor intervention.
Polling checks a peripheral status register how?
A Only at reset
B Repeatedly
C Only by DMA
D Only during interrupt
Answer: B. Repeatedly. Polling repeatedly reads status until a condition is met.
SRAM is often used for small fast what?
A Large optical archives
B Memory buffers
C Magnetic tape
D Printer paper
Answer: B. Memory buffers. SRAM provides fast storage for buffers, caches and small memory structures.
ROM retains data without what?
A Address bus
B Power
C Clock edges
D Instruction decode
Answer: B. Power. Read-only memory is nonvolatile.
EPROM is erased using what type of radiation?
A Infrared heat
B X-rays only
C Visible blue light
D Ultraviolet light
Answer: D. Ultraviolet light. EPROM cells are erased by ultraviolet exposure.
EEPROM can be erased electrically and what?
A Reprogrammed
B Mechanically rotated
C Cooled to zero
D Read only
Answer: A. Reprogrammed. EEPROM can be electrically erased and rewritten.
Flash memory is a form of what?
A Volatile register
B Magnetic tape
C Nonvolatile memory
D Dynamic counter
Answer: C. Nonvolatile memory. Flash stores data without power and can be electrically erased.
An interrupt service routine is entered after what?
A Every instruction
B Interrupt acceptance
C Every memory read
D Power-down only
Answer: B. Interrupt acceptance. The processor transfers control to a handler after accepting an interrupt.
An interrupt priority scheme selects what request first?
A Newest instruction
B Largest address
C Longest data word
D Highest-priority pending
Answer: D. Highest-priority pending. Priority logic chooses which pending interrupt to service.
A memory-mapped peripheral register is accessed using what?
A Only branch instruction
B Only software reset
C Load or store instruction
D DMA command always
Answer: C. Load or store instruction. The CPU reads and writes mapped registers through ordinary memory operations.