The Intel 8085 is how many bits wide internally?
A Four bits
B Sixteen bits
C Thirty-two bits
D Eight bits
Answer: D. Eight bits. The 8085 is an 8-bit microprocessor.
The 8085 address bus is how many bits wide?
A Eight bits
B Ten bits
C Sixteen bits
D Twenty bits
Answer: C. Sixteen bits. The 8085 uses a 16-bit address bus.
The 8085 can address how much byte-addressable memory?
A 8 kilobytes
B 1 megabyte
C 64 kilobytes
D 16 megabytes
Answer: C. 64 kilobytes. A 16-bit address space contains 2^16, or 64K, byte addresses.
The 8085 data bus is how many bits wide?
A Sixteen bits
B Twenty bits
C Four bits
D Eight bits
Answer: D. Eight bits. The 8085 transfers data over an 8-bit bus.
The 8085 accumulator is which register?
A Sixteen-bit PC
B Eight-bit register A
C Five-bit flag
D Four-bit timer
Answer: B. Eight-bit register A. Register A is the accumulator used in many 8085 operations.
The 8085 condition flags include carry and what?
A Zero flag
B Cache flag
C Parity address
D Clock flag
Answer: A. Zero flag. 8085 flags include sign, zero, auxiliary carry, parity and carry.
The 8085 TRAP interrupt is what type?
A Maskable interrupt
B Nonmaskable interrupt
C Software trap only
D Polling input
Answer: B. Nonmaskable interrupt. TRAP is the highest-priority nonmaskable 8085 interrupt.
RST 7.5 is which 8085 interrupt type?
A Level-triggered only
B Nonvectored
C Edge-triggered
D Software-only
Answer: C. Edge-triggered. RST 7.5 is a maskable vectored edge-triggered interrupt.
RST 6.5 is typically which trigger type?
A Edge-triggered
B Level-triggered
C Nonmaskable
D Nonvectored only
Answer: B. Level-triggered. RST 6.5 is a maskable, vectored, level-triggered input.
The 8085 INTR input is what interrupt type?
A Nonvectored maskable
B Nonmaskable vectored
C Software-only
D Edge-triggered only
Answer: A. Nonvectored maskable. INTR is maskable and nonvectored; an external device supplies an instruction during acknowledge.
ALE in the 8085 indicates what?
A Arithmetic logic output
B Interrupt level enable
C Accumulator load edge
D Address latch enable
Answer: D. Address latch enable. ALE strobes an external latch to capture the multiplexed address.
8085 AD0–AD7 lines carry low address then what?
A Clock
B Reset
C Interrupt vector only
D Data
Answer: D. Data. The lower address byte is multiplexed with the data bus.
SID and SOD are used for what communication?
A Serial input and output
B DMA handshaking
C Address decoding
D Clock control
Answer: A. Serial input and output. SID and SOD provide serial data input and output.
The 8085 READY input can insert what?
A Extra address bits
B Wait states
C New registers
D More memory space
Answer: B. Wait states. READY allows slower peripherals to extend bus cycles.
HOLD requests the 8085 to release what?
A System buses
B Accumulator contents
C Clock source
D Flag register
Answer: A. System buses. HOLD requests bus ownership for DMA or another master.
HLDA indicates the processor has done what?
A Started reset
B Cleared flags
C Acknowledged HOLD
D Fetched interrupt vector
Answer: C. Acknowledged HOLD. HLDA signals that the 8085 has released the buses.
INTA is issued during what operation?
A Memory refresh
B Normal arithmetic
C Stack reset
D Interrupt acknowledge
Answer: D. Interrupt acknowledge. The interrupt acknowledge signal accepts an INTR request.
The 8085 stack pointer is how many bits wide?
A Sixteen bits
B Eight bits
C Five bits
D Twenty bits
Answer: A. Sixteen bits. The 8085 SP can address locations across its 16-bit memory space.
In the 8085, PSW combines accumulator and what?
A Program counter
B Flag register
C Stack pointer
D Instruction register
Answer: B. Flag register. The processor status word consists of accumulator A and flags.
The Intel 8086 is how many bits wide?
A Eight bits
B Twenty bits
C Thirty-two bits
D Sixteen bits
Answer: D. Sixteen bits. The 8086 is a 16-bit microprocessor.
The 8086 address bus can address how much memory?
A One megabyte
B 64 kilobytes
C 16 megabytes
D 4 gigabytes
Answer: A. One megabyte. A 20-bit address space supports 2^20 bytes.
8086 physical address combines segment and what?
A Opcode
B Offset
C Carry flag
D Clock period
Answer: B. Offset. Physical address uses segment base plus offset.
The 8086 BIU handles bus operations and what?
A Arithmetic only
B Floating point only
C Instruction prefetch
D Display output
Answer: C. Instruction prefetch. The bus interface unit handles memory and I/O bus transfers and prefetch.
The 8086 execution unit decodes and what?
A Executes instructions
B Refreshes DRAM
C Controls printer
D Generates address bus only
Answer: A. Executes instructions. The EU decodes instructions and executes arithmetic or logic operations.
The original 8086 prefetch queue holds how many bytes?
A Two bytes
B Four bytes
C Six bytes
D Eight bytes
Answer: C. Six bytes. The 8086 BIU prefetch queue stores six instruction bytes.