A high-priority task takes 2 ms every 5 ms. A low-priority task needs 4 ms; both release at zero. With preemption, when does the low-priority task finish?
A 4 ms
B 6 ms
C 8 ms
D 10 ms
Answer: C. 8 ms. The high task runs 0-2 and 5-7 ms; the low task finishes its four milliseconds at 8 ms.
Tasks require 1 ms every 4 ms and 2 ms every 5 ms. What is their combined utilization?
A 65%
B 45%
C 55%
D 80%
Answer: A. 65%. Utilization is 1/4 + 2/5 = 0.65.
What mechanism temporarily boosts a mutex holder blocking a higher-priority task?
A Clock stretching
B DMA chaining
C Priority inheritance
D Time slicing
Answer: C. Priority inheritance. Priority inheritance reduces the duration of priority inversion.
During I2C arbitration, a controller sends high but reads low on SDA. What happened?
A It won arbitration
B A stop completed
C The clock doubled
D It lost arbitration
Answer: D. It lost arbitration. The observed low disagrees with its high, so another controller controls the bus.
An I2C target needs more time and holds SCL low. What is this called?
A Address parity
B Bus termination
C Clock stretching
D Flash paging
Answer: C. Clock stretching. A device may delay transfer progress by holding the clock line low.
Two SPI devices use different CPOL/CPHA settings. What is the likely symptom?
A Incorrect sampled bits
B Higher ADC resolution
C Automatic address ACK
D Reduced flash wear
Answer: A. Incorrect sampled bits. A phase or polarity mismatch changes when bits are sampled.
A UART receiver’s baud setting differs substantially from the transmitter. What may result?
A DMA arbitration
B I2C ACK
C ADC clipping
D Framing errors
Answer: D. Framing errors. Sampling at the wrong times can misread data or the stop bit.
A 16-bit tick counter was 65530 and is now 4. How many ticks elapsed after one wrap?
A 10 ticks
B 4 ticks
C 6 ticks
D 65530 ticks
Answer: A. 10 ticks. Six ticks reach zero and four more reach four, totaling ten.
DMA has filled RAM, but a cached CPU read still shows old data. What maintenance is needed before reading?
A Invalidate cache lines
B Clean cache lines
C Raise UART baud
D Erase firmware
Answer: A. Invalidate cache lines. Invalidation discards stale cached copies so the CPU reads DMA’s data.
Before DMA reads a CPU-modified cached transmit buffer, what action is needed?
A Invalidate only
B Clean cache lines
C Clear UART parity
D Reset the ADC
Answer: B. Clean cache lines. Cleaning writes dirty CPU cache data to RAM for DMA to read.
A windowed watchdog is fed before its permitted window. What can happen?
A Immediate reset
B Timer pauses
C Baud doubles
D Nothing changes
Answer: A. Immediate reset. Window mode detects service that is too early as well as too late.
An unconfirmed trial firmware image fails after reboot. What should a revert-capable bootloader do?
A Erase both images
B Ignore validation
C Restore prior image
D Overclock the CPU
Answer: C. Restore prior image. A trial update can revert if the application does not confirm it.
What does checking a firmware image’s digital signature primarily establish?
A ADC accuracy
B Authenticity
C Power efficiency
D Timing jitter
Answer: B. Authenticity. Signature verification checks that an image was signed by a trusted key.
Why keep a previous working image during a firmware update?
A Increase CPU clock
B Recovery after failure
C Eliminate SRAM
D Improve PWM duty
Answer: B. Recovery after failure. A second image allows recovery when the new image is invalid or interrupted.
Why is a CRC alone insufficient to authenticate firmware?
A Too many bits
B Needs a timer
C Only checks RAM
D No secret key
Answer: D. No secret key. A CRC detects accidental changes, but anyone can recompute it after modification.
A critical section masks interrupts for 4 ms, but an interrupt must respond within 2 ms. What risk follows?
A Faster response
B Higher resolution
C Automatic rollback
D Deadline miss
Answer: D. Deadline miss. Masking interrupts can postpone service beyond the response deadline.
On a priority-enabled Cortex-M, which interrupt can preempt a running lower-priority handler?
A Lower-priority interrupt
B Higher-priority interrupt
C Disabled interrupt
D Completed interrupt
Answer: B. Higher-priority interrupt. A pending interrupt of higher urgency may nest within the handler.
What Cortex-M feature reduces overhead between back-to-back interrupt handlers?
A Flash wear leveling
B Tail chaining
C Clock stretching
D UART parity
Answer: B. Tail chaining. Tail chaining avoids unnecessary return and re-entry work.
A task’s stack high-water mark becomes very small. What does that indicate?
A Large free heap
B High ADC gain
C Low stack margin
D Slow UART clock
Answer: C. Low stack margin. The minimum observed unused stack is approaching zero.
An ISR tries to enqueue data, but the queue is full. What must its code handle?
A Guaranteed delivery
B Automatic flash copy
C Clock inversion
D Send failure
Answer: D. Send failure. A nonblocking send can fail when no queue slot is available.
High source impedance makes ADC sampling inaccurate. Which adjustment may help?
A Shorter acquisition time
B Higher UART baud
C Longer acquisition time
D Smaller RAM stack
Answer: C. Longer acquisition time. The sampling capacitor needs sufficient time to settle through the source impedance.
Before sampling, which circuit attenuates frequencies that would alias into the band?
A Digital high-pass filter
B UART receiver
C Flash controller
D Analog low-pass filter
Answer: D. Analog low-pass filter. An analog anti-alias filter limits high-frequency input before conversion.
Task X locks A then B; task Y locks B then A. What practice prevents their circular wait?
A Consistent lock order
B More polling
C Higher baud
D Shorter ADC reference
Answer: A. Consistent lock order. Acquiring shared locks in the same order removes this deadlock pattern.
Release times vary around a nominal periodic schedule. What is that variation called?
A Quantization
B Jitter
C Hysteresis
D Parity
Answer: B. Jitter. Jitter describes deviations from intended event timing.
A periodic RTOS task should avoid drift from variable execution time. Schedule delays relative to what?
A Previous release time
B Current finish time
C UART start bit
D Last ADC code
Answer: A. Previous release time. Delay-until scheduling uses an absolute periodic release reference.