Difficulty: Medium
How many distinct output codes does a 12-bit ADC have?
A 1024
B 2048
C 4096
D 8192
Answer: C. 4096. Twelve bits encode 2^12 = 4096 values.
With a 3.3 V reference, an ideal 12-bit ADC step is approximately what?
A 3.3 mV
B 8.06 mV
C 0.806 mV
D 0.0806 mV
Answer: C. 0.806 mV. One ideal LSB is 3.3 V divided by 4096.
A 1 MHz timer clock is divided by 8. What is its tick rate?
A 8 kHz
B 125 kHz
C 500 kHz
D 8 MHz
Answer: B. 125 kHz. The prescaler divides 1,000,000 ticks per second by 8.
For a 2 ms PWM period at 25% duty, how long is the high interval?
A 0.25 ms
B 0.5 ms
C 1 ms
D 1.5 ms
Answer: B. 0.5 ms. The high time is 25% of the 2 ms period.
An 8N1 UART frame carries eight data bits. How many bits per frame?
A 10 bits
B 8 bits
C 9 bits
D 11 bits
Answer: A. 10 bits. A start and a stop bit add two bits to eight data bits.
At 9600 baud using 8N1, the ideal maximum is how many bytes per second?
A 1200
B 9600
C 96
D 960
Answer: D. 960. Each byte occupies ten serial bits, so 9600/10 = 960.
After an I2C address, a NACK is received. What should software infer?
A Data is encrypted
B Clock doubled
C DMA completed
D Address not acknowledged
Answer: D. Address not acknowledged. The addressed transfer was not acknowledged; verify the device and bus.
What can an SPI controller do while sending each bit?
A Receive another bit
B Erase flash
C Reset the target
D Measure voltage
Answer: A. Receive another bit. Separate data-in and data-out paths permit simultaneous transfer.
An ISR receives sensor bytes requiring lengthy parsing. Where should parsing run?
A Worker task
B Inside the ISR
C Reset handler
D Clock generator
Answer: A. Worker task. Queue the bytes and defer extensive processing to task context.
Which RTOS object is suitable for signaling a task that an event occurred?
A Mutex
B DAC
C Clock divider
D Binary semaphore
Answer: D. Binary semaphore. A binary semaphore can synchronize a task with an interrupt event.
Two tasks write the same peripheral. What protects the critical section?
A ADC
B Watchdog
C Mutex
D Bootloader
Answer: C. Mutex. A mutex provides exclusive ownership while shared hardware is accessed.
A high-priority task waits for a lock held by a low-priority task. What occurs?
A Clock stretching
B Bus arbitration
C Priority inversion
D Flash retention
Answer: C. Priority inversion. The higher-priority task cannot proceed until the lower-priority holder releases the lock.
During DMA transfer, what useful CPU activity may continue?
A CPU copying every byte
B Other processing
C Manual pin rewiring
D Flash erasure only
Answer: B. Other processing. DMA moves data while the processor can execute unrelated work.
In a circular FIFO buffer, where does the write index go after the last slot?
A First slot
B Middle slot
C Previous slot
D Unused memory
Answer: A. First slot. The index wraps to the beginning of the allocated ring.
A peripheral register may change outside current code flow. Which qualifier prevents cached reads in C?
A static
B const
C inline
D volatile
Answer: D. volatile. Volatile tells the compiler that accesses are observable and must be performed.
Two contexts increment one shared counter. What prevents lost updates?
A Volatile alone
B Atomic operation
C Longer delay
D Higher baud
Answer: B. Atomic operation. A read-modify-write increment needs atomicity or suitable synchronization.
Before using a memory-mapped peripheral, what may need enabling?
A UART parity
B Peripheral clock
C Heap compaction
D PWM output
Answer: B. Peripheral clock. Many MCUs gate peripheral clocks until explicitly enabled.
A signal contains frequencies up to 2 kHz. What sampling rate exceeds Nyquist?
A 1 kHz
B 2 kHz
C 4 kHz
D 5 kHz
Answer: D. 5 kHz. The sampling frequency must exceed twice the highest signal frequency.
What does interrupt latency measure?
A Event-to-handler delay
B Firmware image size
C ADC full scale
D Queue depth
Answer: A. Event-to-handler delay. It is the time from an interrupt request to handler execution.
A state machine is in IDLE and receives START. What should determine the next state?
A Transition rule
B Flash capacity
C UART parity
D Timer width
Answer: A. Transition rule. Defined state and event transitions determine the resulting state.
What is the signed range of an 8-bit two’s-complement integer?
A 0 to 255
B -127 to 128
C -128 to 127
D -256 to 255
Answer: C. -128 to 127. Eight signed bits have range -2^7 through 2^7-1.
How many ticks occur before a free-running 16-bit counter wraps?
A 32768
B 65535
C 131072
D 65536
Answer: D. 65536. A 16-bit counter has 2^16 states, counting 0 through 65535.
A watchdog expires in 100 ms, but is fed every 150 ms. What is expected?
A Timeout reset
B No reset
C Baud change
D ADC saturation
Answer: A. Timeout reset. The feed interval exceeds the configured timeout.
Polling occurs every 10 ms. What is the approximate worst wait to notice an event?
A 1 ms
B 100 ms
C 10 ms
D 0 ms
Answer: C. 10 ms. An event arriving just after a check waits nearly one full poll interval.
Of 8 KB RAM, stack uses 2 KB and heap uses 3 KB. What remains?
A 2 KB
B 3 KB
C 5 KB
D 8 KB
Answer: B. 3 KB. Eight minus two minus three leaves three kilobytes.