CMOS logic uses which transistor pair?
A NMOS and PMOS
B NPN and PNP only
C JFET and SCR
D LED and photodiode
Answer: A. NMOS and PMOS. CMOS logic combines complementary n-channel and p-channel MOSFETs.
Static CMOS draws little steady-state power except leakage and what?
A Mechanical power
B Switching power
C Hydraulic power
D Acoustic power
Answer: B. Switching power. Most CMOS dynamic power is consumed during switching.
TTL logic is based on which device family?
A MOSFETs only
B Optical fibers
C Bipolar transistors
D Relays only
Answer: C. Bipolar transistors. Transistor-transistor logic uses bipolar junction transistors.
Noise margin measures tolerance to what?
A Clock frequency
B Signal voltage noise
C Memory size
D Fan-in only
Answer: B. Signal voltage noise. Noise margin quantifies how much voltage disturbance can be tolerated.
Dynamic power in CMOS increases with frequency and what?
A Memory address
B Fan-out only
C Clock label
D Capacitance
Answer: D. Capacitance. Dynamic power is proportional to switching activity, capacitance and frequency.
An open-collector output requires what external component?
A Pull-down capacitor
B Clock crystal
C Transformer
D Pull-up resistor
Answer: D. Pull-up resistor. The output transistor can pull low but needs a pull-up to create a high level.
A pull-up resistor biases a signal toward what?
A Logic low
B High impedance only
C Logic high
D Negative voltage always
Answer: C. Logic high. A pull-up provides a default high logic level.
A Schmitt trigger provides what input behavior?
A Linear amplification only
B Hysteresis
C Memory storage
D Clock division
Answer: B. Hysteresis. Hysteresis creates separate switching thresholds to reject noisy transitions.
A synchronizer reduces metastability risk when crossing what?
A Power domains only
B Memory pages
C Clock domains
D Logic gates only
Answer: C. Clock domains. Synchronizer flip-flops reduce the chance of metastability propagating across clock domains.
An FPGA implements logic using configurable what?
A Hydraulic valves
B Mechanical relays only
C Hard disks
D Look-up tables
Answer: D. Look-up tables. FPGA logic cells commonly use LUTs and programmable interconnect.
A CPLD is a programmable logic device with what structure?
A Logic blocks and interconnect
B Only one transistor
C A mechanical cam
D Optical memory only
Answer: A. Logic blocks and interconnect. CPLDs combine programmable logic blocks linked by routing resources.
A PAL typically has programmable AND logic and what OR structure?
A Programmable OR always
B No OR gates
C Fixed OR
D Analog OR only
Answer: C. Fixed OR. A programmable array logic device uses a programmable AND plane and fixed OR plane.
A PLA has programmable AND and what planes?
A Clock planes
B Power planes
C Memory planes
D OR planes
Answer: D. OR planes. A PLA provides programmable product-term and sum-term arrays.
A ROM can implement a combinational function by storing what?
A Truth table outputs
B Clock edges
C Tool offsets
D Machine states only
Answer: A. Truth table outputs. A ROM maps input addresses to stored function outputs.
HDL describes digital circuits using what?
A Textual hardware models
B Only circuit photos
C Mechanical drawings only
D User stories only
Answer: A. Textual hardware models. Hardware description languages model behavior or structure of digital systems.
Verilog continuous assignment commonly uses which keyword?
A always_ff only
B wireless
C assign
D module_end
Answer: C. assign. The assign statement drives a continuous net expression.
Logic synthesis converts HDL into what implementation?
A Printed manual
B Gate-level network
C Mechanical assembly
D Analog sensor
Answer: B. Gate-level network. Synthesis maps hardware descriptions to logic cells and connections.
A test vector specifies input values and expected what?
A Machine speed
B Memory price
C Outputs
D Tool length
Answer: C. Outputs. A test vector provides stimulus and expected response for verification.
A scan chain improves what digital testability?
A Clock frequency
B Internal state access
C Logic voltage
D Memory capacity
Answer: B. Internal state access. Scan chains shift internal flip-flop states for structural testing.
Gray code is useful when reducing what between adjacent values?
A Logic levels
B Memory pages
C Clock cycles
D Bit transitions
Answer: D. Bit transitions. Only one bit changes between adjacent Gray-code values.
A synchronous design updates state on what event?
A Clock edge
B Any signal change
C Power loss
D Data bus idle
Answer: A. Clock edge. Synchronous logic uses a clock edge to update state.
A timing constraint specifies required setup and what?
A Memory color
B Clock relationship
C Gate count only
D Input format
Answer: B. Clock relationship. Timing constraints describe clock periods, I/O delays and path requirements.
A logic analyzer captures digital signals over what?
A Time
B Mass
C Temperature only
D Surface area
Answer: A. Time. Logic analyzers record multiple digital channels against time.
A metastability MTBF estimate depends on frequency and what?
A Gate color
B Memory capacity
C Output load only
D Resolution time
Answer: D. Resolution time. MTBF improves with more resolution time and depends on clock and data activity.
A debouncer prevents multiple transitions from what input?
A Mechanical switch
B Clock oscillator
C Memory bus
D Logic synthesis
Answer: A. Mechanical switch. Mechanical contacts can chatter, so debouncing filters rapid transitions.