A latch is transparent during what condition?
A Only a clock edge
B Power-off
C Active enable level
D Any reset only
Answer: C. Active enable level. A level-sensitive latch passes input while enable is active.
A D flip-flop captures input at what event?
A Clock edge
B Any time
C Power-up only
D Data transition only
Answer: A. Clock edge. An edge-triggered D flip-flop samples D at a clock edge.
A JK flip-flop toggles when J and K are what?
A Both zero
B J only one
C Both one
D K only one
Answer: C. Both one. For J=K=1, a JK flip-flop toggles its state.
An SR latch has which problematic input combination?
A Both inactive
B Set only
C Set and reset active
D Reset only
Answer: C. Set and reset active. Simultaneously asserting set and reset can produce an invalid or forbidden state.
A T flip-flop toggles when T equals what?
A Zero
B High impedance
C Clock only
D One
Answer: D. One. T=1 causes a toggle on the active clock event.
Setup time requires input stability before what?
A Reset release only
B Power-down
C Clock edge
D Output transition
Answer: C. Clock edge. Setup time is the minimum stable interval before a sampling edge.
Hold time requires input stability after what?
A Power-up
B Reset assertion
C Output settling only
D Clock edge
Answer: D. Clock edge. Hold time is the minimum stable interval after a sampling edge.
Clock-to-Q delay is measured from clock edge to what?
A Input change
B Reset release
C Power-up
D Output change
Answer: D. Output change. Clock-to-Q is the delay between active clock edge and flip-flop output response.
Metastability can occur when setup or hold time is what?
A Violated
B Always satisfied
C Clock frequency is zero
D Output is buffered
Answer: A. Violated. Timing violations can leave a storage element temporarily between logic states.
A synchronous reset takes effect on what?
A Any time immediately
B Clock edge
C Power-on only
D Input data transition
Answer: B. Clock edge. Synchronous reset is sampled with the clock.
An asynchronous set can force state independent of what?
A Supply voltage
B Clock edge
C Reset signal
D Logic input
Answer: B. Clock edge. Asynchronous set acts without waiting for a clock event.
A shift register moves data by what action?
A Analog conversion
B Address decoding
C Power switching
D Clocked bit shifts
Answer: D. Clocked bit shifts. A shift register moves stored bits left or right on clock events.
A modulo-N counter repeats after how many states?
A N states
B 2N states
C N squared states
D One state only
Answer: A. N states. A mod-N counter cycles through N distinct states.
A ring counter circulates what pattern?
A Carry bits only
B Memory addresses
C Shift-register state
D Analog voltage
Answer: C. Shift-register state. A ring counter feeds the last shift-register output back to the first input.
A Johnson counter feeds back what signal?
A Inverted last output
B First input only
C Carry-out
D Clock enable
Answer: A. Inverted last output. A Johnson counter feeds the complement of the last stage to the first.
A ripple counter clocks each stage from what?
A Previous stage output
B Common external clock only
C Reset line
D Data bus
Answer: A. Previous stage output. In an asynchronous ripple counter, stages trigger successively from prior outputs.
A synchronous counter applies clock to what stages?
A All flip-flops
B Only first stage
C Only reset input
D Output decoder
Answer: A. All flip-flops. All flip-flops share the same clock edge in a synchronous counter.
A finite-state machine consists of states and what?
A Only data bytes
B Transitions
C Memory pages
D Analog filters
Answer: B. Transitions. FSM behavior is defined by states, transitions and outputs.
A Moore machine output depends on what?
A Current state
B Input only
C Previous input only
D Clock frequency only
Answer: A. Current state. Moore outputs are functions of the current state.
A Mealy machine output depends on state and what?
A Reset history only
B Current input
C Clock frequency
D Memory size
Answer: B. Current input. Mealy outputs depend on current state and current input.
State encoding assigns bit patterns to what?
A Input pins
B FSM states
C Clock cycles
D Output voltages only
Answer: B. FSM states. State encoding represents each abstract state using binary bits.
A sequence detector recognizes what input pattern?
A Clock frequency
B Specified bit sequence
C Memory size
D Output voltage
Answer: B. Specified bit sequence. A sequence detector reports when a target bit pattern occurs.
A clock divider generates output at what rate?
A Higher voltage
B Higher frequency always
C Lower frequency
D Same phase only
Answer: C. Lower frequency. A divider reduces input clock frequency by an integer or programmed ratio.
Clock skew is the difference in clock arrival time at what?
A Data inputs
B Power rails
C Memory files
D Circuit locations
Answer: D. Circuit locations. Clock skew measures timing difference between clock paths.
A reset state defines the FSM condition after what?
A Every data input
B Each clock cycle
C A cache miss
D Reset event
Answer: D. Reset event. Reset initializes the sequential circuit to a known state.