The Von Neumann architecture uses shared memory for instructions and what?
A Power supply
B Network cables
C Monitor pixels
D Data
Answer: D. Data. Von Neumann systems share a memory path for instructions and data.
Harvard architecture separates instruction and what memory?
A Cache tags
B Registers
C Virtual address only
D Data memory
Answer: D. Data memory. Harvard architecture provides separate instruction and data memories or buses.
The instruction cycle commonly begins by fetching from what?
A Printer
B Keyboard
C Power supply
D Memory
Answer: D. Memory. The processor fetches an instruction from memory before decoding and execution.
The program counter holds the address of what?
A Last data byte
B Current screen pixel
C Next instruction
D Printer queue
Answer: C. Next instruction. The PC points to the next instruction to fetch.
The instruction register holds what currently?
A Next memory address only
B Input voltage
C Fetched instruction
D Cache capacity
Answer: C. Fetched instruction. The instruction register stores the instruction being decoded or executed.
Cache locality includes temporal locality and what?
A Boolean locality
B Address polarity
C Spatial locality
D Bus locality
Answer: C. Spatial locality. Temporal locality reuses recent data; spatial locality accesses nearby data.
A cache hit occurs when requested data is found in what?
A Disk only
B Cache
C Printer buffer
D Network router
Answer: B. Cache. A cache hit avoids fetching the block from slower memory.
Virtual memory gives processes an abstraction of what?
A Infinite CPU speed
B Large address space
C More physical cores
D Fixed registers only
Answer: B. Large address space. Virtual memory maps process addresses to physical memory and storage.
Paging divides virtual memory into fixed-size what?
A Pages
B Segments of variable size only
C Files
D Instructions only
Answer: A. Pages. Paging maps virtual pages onto physical frames.
A TLB caches recent what?
A CPU instructions only
B Disk files
C Network packets
D Address translations
Answer: D. Address translations. A translation lookaside buffer speeds virtual-to-physical address translation.
DMA transfers data between devices and memory with less what?
A Storage capacity
B CPU involvement
C Bus width
D Network access
Answer: B. CPU involvement. Direct memory access offloads bulk transfers from the CPU.
An interrupt asks the processor to handle what?
A A file format
B A display pixel
C A memory capacity
D An event
Answer: D. An event. Interrupts signal events requiring processor attention.
Polling checks device status by what method?
A Repeatedly reading status
B Waiting for interrupt only
C Changing memory size
D Resetting CPU clock
Answer: A. Repeatedly reading status. Polling repeatedly queries a device to determine whether it needs service.
Bus arbitration decides which bus master gets what?
A Memory capacity
B Bus access
C Clock speed
D Interrupt vector only
Answer: B. Bus access. Arbitration resolves competing requests for shared bus ownership.
Instruction pipelining overlaps what?
A Power cycles
B Memory modules
C Execution stages
D User sessions
Answer: C. Execution stages. Pipelining increases throughput by overlapping instruction processing stages.
A data hazard occurs when instructions have what dependency?
A Conflicting data access
B Different colors
C Unrelated files
D Separate networks
Answer: A. Conflicting data access. Data hazards arise when an instruction depends on another instruction’s result.
Branch prediction guesses the outcome of what?
A Conditional branch
B Memory write
C Disk seek
D Arithmetic sum
Answer: A. Conditional branch. Branch prediction reduces pipeline stalls by predicting control flow.
A superscalar processor can issue multiple what?
A Bytes per disk
B Networks per bus
C Instructions per cycle
D Programs per user only
Answer: C. Instructions per cycle. Superscalar designs issue more than one instruction in a clock cycle.
A multicore processor contains multiple what?
A Processing cores
B Power supplies
C Hard drives
D Operating systems only
Answer: A. Processing cores. Multicore chips integrate two or more processor cores.
Endianness defines byte order in what?
A Instruction pipeline
B Multi-byte values
C Cache replacement
D Bus arbitration
Answer: B. Multi-byte values. Endianness specifies which byte is stored at the lowest address.
Memory-mapped I/O assigns devices what?
A CPU cores
B Cache lines
C Memory addresses
D File names
Answer: C. Memory addresses. Memory-mapped devices are accessed through addresses in the system memory space.
The address bus identifies what destination?
A Data value
B Control signal only
C Clock phase
D Memory or device location
Answer: D. Memory or device location. Address lines select a location or device endpoint.
The data bus carries what between components?
A Data values
B Addresses only
C Control commands only
D Clock pulses only
Answer: A. Data values. The data bus transfers information payloads among components.
Amdahl’s law limits speedup based on what fraction?
A Serial fraction
B Cache size
C Bus width
D Memory latency only
Answer: A. Serial fraction. Amdahl’s law shows nonparallelizable work limits total speedup.
Memory latency is the delay before data becomes what?
A Compressed
B Available
C Encrypted
D Deleted
Answer: B. Available. Latency measures time from request to usable response.